
/*----------------------------------------------------------------------------
 * Copyright (c) <2013-2015>, <Huawei Technologies Co., Ltd>
 * All rights reserved.
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 * 1. Redistributions of source code must retain the above copyright notice, this list of
 * conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright notice, this list
 * of conditions and the following disclaimer in the documentation and/or other materials
 * provided with the distribution.
 * 3. Neither the name of the copyright holder nor the names of its contributors may be used
 * to endorse or promote products derived from this software without specific prior written
 * permission.
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *---------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
 * Notice of Export Control Law
 * ===============================================
 * Huawei LiteOS may be subject to applicable export control laws and regulations, which might
 * include those applicable to Huawei LiteOS of U.S. and the country in which you are located.
 * Import, export and usage of Huawei LiteOS in any manner by you shall be in compliance with such
 * applicable export control laws and regulations.
 *---------------------------------------------------------------------------*/
#include "stdio.h"
#include "stdlib.h"
#include "los_atomic.h"
#include "hisoc/usb3.h"
#include "asm/hal_platform_ints.h"

extern VOID LOS_Mdelay(UINT32 msecs);

#define REG_GUSB3PIPECTL0   IO_ADDRESS(CONFIG_HIUSB_XHCI_IOBASE + 0xc2c0)
#define PCS_SSP_SOFT_RESET    (0x1U << 31)
#define REG_GUSB2PHYCFG0    IO_ADDRESS(CONFIG_HIUSB_XHCI_IOBASE + 0xC200)
#define BIT_U2_FREECLK_EXISTS (0x1 << 30)
#define BIT_UTMI_ULPI         (0x1U << 4)
#define BIT_UTMI_8_16         (0x1U << 3)
#define GTXTHRCFG   IO_ADDRESS(CONFIG_HIUSB_XHCI_IOBASE + 0xc108)
#define GRXTHRCFG   IO_ADDRESS(CONFIG_HIUSB_XHCI_IOBASE + 0xc10c)
#define REG_GCTL    IO_ADDRESS(CONFIG_HIUSB_XHCI_IOBASE + 0xc110)
#define U2RSTECN    (0x1 << 16)

#define USB3_PERI_CRG97   IO_ADDRESS(CRG_REG_BASE + 0x184)
#define USB3_PERI_CRG98   IO_ADDRESS(CRG_REG_BASE + 0x188)
#define USB3_PERI_CRG100   IO_ADDRESS(CRG_REG_BASE + 0x190)
#define COMBPHY0_REFCLK_SEL (0x1U << 9)
#define COMBPHY1_REFCLK_SEL (0x1U << 25)
#define COMBPHY0_REF_CLKEN  (0x1U << 8)
#define COMBPHY1_REF_CLKEN  (0x1U << 24)
#define COMBPHY0_SRST_REQ   (0x1U << 0)
#define COMBPHY1_SRST_REQ   (0x1U << 16)
#define USB3_1_VCC_SRST_REQ (0x1U << 0)
#define USB3_0_VCC_SRST_REQ (0x1U << 16)
#define USB3_1_UTMI_CLKSEL    BIT(13)
#define USB3_0_UTMI_CLKSEL    BIT(29)
#define USB3_1_UTMI_CLKEN    BIT(12)
#define USB3_0_UTMI_CLKEN    BIT(28)
#define USB3_1_PIPE_CLKEN   BIT(11)
#define USB3_0_PIPE_CLKEN   BIT(27)
#define USB3_1_SUSPEND_CLKEN    BIT(10)
#define USB3_0_SUSPEND_CLKEN    BIT(26)
#define USB3_1_REF_CLKEN    BIT(9)
#define USB3_0_REF_CLKEN    BIT(25)
#define USB3_1_BUS_CLKEN    BIT(8)
#define USB3_0_BUS_CLKEN    BIT(24)

#define TX_MARGIN_MASK  (0x7 << 3)
#define TX_MARGIN_VAL   (0x2 << 3)
#define USB3_PHY   IO_ADDRESS(MISC_REG_BASE + 0x88)
#define COMBO_PHY_TX_DEEMP_MASK (0x7 << 12)
#define COMBO_PHY_TX_DEEMP_VAL  (0x1 << 12)

#define USB2_PHY1_REF_CLKEN   (0x1U << 4)
#define USB2_PHY0_REF_CLKEN   (0x1U << 5)

#define USB2_PHY1_SRST_TREQ  (0x1U << 2)
#define USB2_PHY0_SRST_TREQ  (0x1U << 3)
#define USB2_PHY1_SRST_REQ  (0X1U << 0)
#define USB2_PHY0_SRST_REQ  (0X1U << 1)

static long dev_open_cnt = 0;
static int otg_usbdev_stat = 0;

void hiusb3_host2device(void)
{
    unsigned int reg;

    reg = GET_UINT32(REG_GCTL);
    reg &= ~(0x3<<12);
    reg |= (0x1<<13); /*[13:12] 01: Host; 10: Device; 11: OTG*/
    WRITE_UINT32(reg, REG_GCTL);
    LOS_Udelay(20);
}

static int hisi_usb3_phy_config(void)
{
    unsigned int reg;

    reg = GET_UINT32(REG_GUSB3PIPECTL0);
    reg |= PCS_SSP_SOFT_RESET;
    WRITE_UINT32(reg, REG_GUSB3PIPECTL0);

    reg = GET_UINT32(REG_GUSB2PHYCFG0);
    reg |= BIT_U2_FREECLK_EXISTS;
    reg &= ~(BIT_UTMI_ULPI);
    reg &= ~(BIT_UTMI_8_16);
    WRITE_UINT32(reg, REG_GUSB2PHYCFG0);
    LOS_Udelay(20);

    reg = GET_UINT32(REG_GCTL);
    reg &= ~(0x3<<12);
    reg |= (0x1<<12); /*[13:12] 01: Host; 10: Device; 11: OTG*/

    reg &= ~U2RSTECN;
    WRITE_UINT32(reg, REG_GCTL);
    LOS_Udelay(20);

    reg = GET_UINT32(REG_GUSB3PIPECTL0);
    reg &= ~(PCS_SSP_SOFT_RESET);
    reg &= ~(1<<17);       /* disable suspend */
    WRITE_UINT32(reg, REG_GUSB3PIPECTL0);
    LOS_Udelay(100);

    WRITE_UINT32(0x23100000, GTXTHRCFG);
    WRITE_UINT32(0x23180000, GRXTHRCFG);
    LOS_Udelay(200);

    return 0;
}

static int hisi_usb3_phy_power_off(void)
{
    unsigned int reg;
    if (LOS_AtomicDecRet((void *)&dev_open_cnt) == 0) {
        reg = GET_UINT32(USB3_PERI_CRG98);
        reg &= ~(COMBPHY0_REF_CLKEN);
        reg &= ~(COMBPHY1_REF_CLKEN);
        reg |= COMBPHY0_SRST_REQ;
        reg |= COMBPHY1_SRST_REQ;
        WRITE_UINT32(reg, USB3_PERI_CRG98);
        LOS_Msleep(10);

        reg = GET_UINT32(USB3_PERI_CRG100);
        reg |=  USB3_1_VCC_SRST_REQ;
        reg |= USB3_0_VCC_SRST_REQ;
        WRITE_UINT32(reg, USB3_PERI_CRG100);
        LOS_Mdelay(10);
    }
    return 0;
}

static int hisi_usb3_phy_power_on(void)
{
    unsigned int reg;

    if (LOS_AtomicIncRet((void *)&dev_open_cnt) == 1) {

        WRITE_UINT32(0x635f3 , MISC_REG_BASE + 0x138);
        LOS_Udelay(200);
        WRITE_UINT32(0x635f3 , MISC_REG_BASE + 0x144);
        LOS_Udelay(200);

        WRITE_UINT32(0x36b62e00, MISC_REG_BASE + 0x134);
        LOS_Udelay(200);
        WRITE_UINT32(0x36b62e00, MISC_REG_BASE + 0x140);
        LOS_Udelay(200);

        reg = GET_UINT32(USB3_PERI_CRG97);
        reg &= ~(USB2_PHY0_SRST_TREQ);
        reg &= ~(USB2_PHY1_SRST_TREQ);
        WRITE_UINT32(reg, USB3_PERI_CRG97);

        reg = GET_UINT32(USB3_PERI_CRG97);
        reg &= ~(USB2_PHY0_SRST_REQ);
        reg &= ~(USB2_PHY1_SRST_REQ);
        /*Revoke U2PHY0 and U2PHY1 reset*/
        WRITE_UINT32(reg, USB3_PERI_CRG97);
        LOS_Mdelay(1);

        reg = GET_UINT32(USB3_PERI_CRG97);
        reg |= USB2_PHY0_REF_CLKEN;
        reg |= USB2_PHY1_REF_CLKEN;
        WRITE_UINT32(reg, USB3_PERI_CRG97);
        LOS_Udelay(200);

        reg = GET_UINT32(USB3_PERI_CRG98);
        reg |= COMBPHY0_REFCLK_SEL;
        reg |= COMBPHY1_REFCLK_SEL;
        /*U3 controller UTMI clock source selection U2PHY supply*/
        WRITE_UINT32(reg, USB3_PERI_CRG98);

        reg = GET_UINT32(USB3_PERI_CRG98);
        reg |= COMBPHY0_REF_CLKEN;
        reg |= COMBPHY1_REF_CLKEN;
        /*Select COMPHYPHY reference clock 25M*/
        WRITE_UINT32(reg, USB3_PERI_CRG98);
        LOS_Udelay(200);

        reg = GET_UINT32(USB3_PERI_CRG98);
        reg &= ~(COMBPHY0_SRST_REQ);
        reg &= ~(COMBPHY1_SRST_REQ);
        /*Select COMPHY clock gating*/
        WRITE_UINT32(reg, USB3_PERI_CRG98);
        LOS_Mdelay(1);

        reg = GET_UINT32(USB3_PERI_CRG100);
        reg &= ~(USB3_1_UTMI_CLKSEL | USB3_0_UTMI_CLKSEL);
        reg |= (USB3_1_UTMI_CLKEN | USB3_0_UTMI_CLKEN);
        reg |= (USB3_1_PIPE_CLKEN | USB3_0_PIPE_CLKEN);
        reg |= (USB3_1_SUSPEND_CLKEN | USB3_0_SUSPEND_CLKEN);
        reg |= (USB3_1_REF_CLKEN | USB3_0_REF_CLKEN);
        reg |= (USB3_1_BUS_CLKEN | USB3_0_BUS_CLKEN);
        reg &= ~(USB3_1_VCC_SRST_REQ);
        reg &= ~(USB3_0_VCC_SRST_REQ);
        /*COMPHY port soft reset mode selection is controlled by PERI_CRG45 [0]*/
        WRITE_UINT32(reg, USB3_PERI_CRG100);
        LOS_Mdelay(1);

        (void)hisi_usb3_phy_config();

        LOS_Mdelay(10);
    }
    return 0;
}

void hiusb3_start_hcd(void)
{
    (void)hisi_usb3_phy_power_on();
}
void hiusb3_stop_hcd(void)
{
    (void)hisi_usb3_phy_power_off();
}

void hiusb3_reset_hcd(void)
{
}

int hiusb_is_device_mode(void)
{
    return (otg_usbdev_stat == 1);
}

void usb_otg_sw_set_device_state(void)
{
    otg_usbdev_stat = 1;
}

void usb_otg_sw_clear_device_state(void)
{
    otg_usbdev_stat = 0;
}

